This application claims the benefit of Korean Patent Application No. 2001-3304, filed on Jan. 19, 2001, which is hereby incorporated by reference in their entirety.
This application incorporates by reference in their entirety co-pending U.S. application Ser. No. 09/933,353, mailed via Express Mail No. EF334462230US entitled xe2x80x9cVSB COMMUNICATION SYSTEMxe2x80x9d and Ser. No. 09/933,280, mailed via Express Mail No. EF334462226US entitled xe2x80x9cVSB TRANSMISSION SYSTEM FOR PROCESSING SUPPLEMENTAL TRANSMISSION DATA.xe2x80x9d
1. Field of the Invention
The present invention relates to a digital television reception system, and more particularly, to a 8T-VSB (Vestigial Sideband) reception system resistant to ghost and noise and receiving and decoding supplemental data in addition to MPEG data.
2. Description of the Related Art
The United States of America has employed ATSC 8T-VSB (8 Trellis-Vestigial Sideband) as a standard since 1995, and has been broadcasting in the ATSC 8T-VSB since the later half of 1998. South Korea also has employed the ATSC 8T-VSB as a standard. South Korea started test broadcasting in May 1995, and has since August 2000 put in place a regular test broadcasting system. The advancement of technology allows the transmission of digital television (DTV) in the same 6 MHz bandwidth currently used by NTSC.
FIG. 1 illustrates a block diagram of a conventional ATSC 8T-VSB transmission system 25 (xe2x80x9cVSB transmission systemxe2x80x9d). The VSB transmission system 25 generally comprises a data randomizer 1, Reed-Solomon coder 2, data interleaver 3, Trellis coder 4, multiplexer 5, pilot inserter 6, VSB modulator 7 and RF converter 8.
Referring to FIG. 1, there is a data randomizer 1 for receiving and making random MPEG data (video, audio and ancillary data). The data randomizer 1 receives the MPEG-II data output from an MPEG-II encoder. Although not shown in FIG. 1, the MPEG-II encoder takes baseband digital video and performs bit rate compression using the techniques of discrete cosine transform, run length coding, and bi-directional motion prediction. The MPEG-II encoder then multiplexes this compressed data together with pre-coded audio and any ancillary data that will be transmitted. The result is a stream of compressed MPEG-II data packets with a data frequency of only 19.39 Mbit/Sec. The MPEG-II encoder outputs such data to the data randomizer in serial form. MPEG-II packets are 188 bytes in length with the first byte in each packet always being the sync or header byte. The MPEG-II sync byte is then discarded. The sync byte will ultimately be replaced by the ATSC segment sync in a later stage of processing.
In the VSB transmission system 25, the 8-VSB bit stream should have a random, noise-like signal. The reason being that the transmitted signal frequency response must have a flat noise-like spectrum in order to use the allotted 6 MHz channel space with maximum efficiency. Random data minimizes interference into analog NTSC. In the data randomizer 1, each byte value is changed according to known pattern of pseudo-random number generation. This process is reversed in the VSB receiver in order to recover the proper data values.
The Reed-Solomon coder 2 of the VSB transmission system 25 is used for subjecting the output data of the data randomizer 1 to Reed-Solomon coding and adding a 20 byte parity code to the output data. Reed Solomon encoding is a type of forward error correction scheme applied to the incoming data stream. Forward error correction is used to correct bit errors that occur during transmission due to signal fades, noise, etc. Various types of techniques may be used as the forward error correction process.
The Reed-Solomon coder 2 takes all 187 bytes of an incoming MPEG-II data packet (the sync or header byte has been removed from 188 bytes) and mathematically manipulates them as a block to create a digital sketch of the block contents. This xe2x80x9csketchxe2x80x9d occupies 20 additional bytes which are added at the tail end of the original 187 byte packet. These 20 bytes are known as Reed-Solomon parity bytes. The 20 Reed-Solomon parity bytes for every data packet add redundancy for forward error correction of up to 10 byte errors/packet. Since Reed-Solomon decoders correct byte errors, and bytes can have anywhere from 1 to 8 bit errors within them, a significant amount of error correction can be accomplished in the VSB reception system. The output of the Reed-Solomon coder 2 is 207 bytes (187 plus 20 parity bytes).
The VSB reception system will compare the received 187 byte block to the 20 parity bytes in order to determine the validity of the recovered data. If errors are detected, the receiver can use the parity bytes to locate the exact location of the errors, modify the corrupted bytes, and reconstruct the original information.
The data interleaver 3 interleaves the output data of the Reed-Solomon coder 2. In particular, the data interleaver 3 mixes the sequential order of the data packet and disperses or delays the MPEG-II packet throughout time. The data interleaver 3 then reassembles new data packets incorporating small sections from many different MPEG-II (pre-interleaved) packets. The reassembled packets are 207 bytes each.
The purpose of the data interleaver 3 is to prevent losing of one or more packets due to noise or other harmful transmission environment. By interleaving data into many different packets, even if one packet is completely lost, the original packet may be substantially recovered from information contained in other packets.
The VSB transmission system 25 also has a trellis coder 4 for converting the output data of the data interleaver 3 from byte form into symbol form and for subjecting it to trellis coding. In the trellis coder 4, bytes from the data interleaver 3 are converted into symbols and provided one by one to a plurality of Trellis coders and precoders 32-1 to 32-12, shown in FIG. 7.
Trellis coding is another form of forward error correction. Unlike Reed-Solomon coding, which treated the entire MPEG-II packet simultaneously as a block, trellis coding is an evolving code that tracks the progressing stream of bits as it develops through time.
The trellis coder 4 adds additional redundancy to the signal in the form of more (than four data levels, creating the multilevel (8) data symbols for transmission. For trellis coding, each 8-bit byte is split up into a stream of four, 2-bit words. In the trellis coder 4, each 2-bit input word is compared to the past history of previous 2-bit words. A 3-bit binary code is mathematically generated to describe the transition from the previous 2-bit word to the current one. These 3-bit codes are substituted for the original 2-bit words and transmitted as the eight level symbols of 8-VSB. For every two bits that enter the trellis coder 4, three bits come out.
The trellis decoder in the VSB receiver uses the received 3-bit transition codes to reconstruct the evolution of the data stream from one 2-bit word to the next. In this way, the trellis coder follows a xe2x80x9ctrailxe2x80x9d as the signal moves from one word to the next through time. The power of trellis coding lies in its ability to track a signal""s history through time and discard potentially faulty information (errors) based on a signal""s past and future behavior.
A multiplexer 5 is used for multiplexing a symbol stream from the trellis coder 4 and synchronizing signals. The segment and the field synchronizing signals provide information to the VSB receiver to accurately locate and demodulate the transmitted RF signal. The segment and the field synchronizing signals are inserted after the randomization and error coding stages so as not to destroy the fixed time and amplitude relationships that these signals must possess to be effective. The multiplexer 5 provides the output from the trellis coder 4 and the segment and the field synchronizing signals in a time division manner.
An output packet of the data interleaver 3 comprises the 207 bytes of an interleaved data packet. After trellis coding, the 207 byte segment is stretched out into a baseband stream of 828 eight level symbols. The segment synchronizing signal is a four symbol pulse that is added to the front of each data segment and replaces the missing first byte (packet sync byte) of the original MPEG-II data packet. The segment synchronizing signal appears once every 832 symbols and always takes the form of a positive-negative-positive pulse swinging between the +5 and xe2x88x925 signal levels.
The field synchronizing signal is an entire data segment that is repeated once per field. The field synchronizing signal has a known data symbol pattern of positive-negative pulses and is used by the receiver to eliminate signal ghosts caused by poor reception.
The VSB transmission system 25 also has the pilot inserter 6 for inserting pilot signals into the symbol stream from the multiplexer 5. Similar to the synchronizing signals described above, the pilot signal is inserted after the randomization and error coding stages so as not to destroy the fixed time and amplitude relationships that these signals must possess to be effective.
Before the data is modulated, a small DC shift is applied to the 8T-VSB baseband signal. This causes a small residual carrier to appear at the zero frequency point of the resulting modulated spectrum. This is the pilot signal provided by the pilot inserter 6. This gives the RF PLL circuits in the VSB receiver something to lock onto that is independent of the data being transmitted.
After the pilot signal has been inserted by the pilot inserter 6, the output is subjected to a VSB modulator 7. The VSB modulator 7 modulates the symbol stream from the pilot inserter 6 into an 8 VSB signal of an intermediate frequency band. The VSB modulator 7 provides a filtered (root-raised cosine) IF signal at a standard frequency (44 Mhz in the U.S.), with most of one sideband removed.
In particular, the eight level baseband signal is amplitude modulated onto an intermediate frequency (IF) carrier. The modulation produces a double sideband IF spectrum about the carrier frequency. The total spectrum is too wide to be transmitted in the assigned 6 MHz channel.
The sidelobes produced by the modulation are simply scaled copies of the center spectrum, and the entire lower sideband is a mirror image of the upper sideband. Therefore using a filter, the VSB modulator discards the entire lower sideband and all of the sidelobes in the upper sideband. The remaining signal (upper half of the center spectrum) is further eliminated in one-half by using the Nyquist filter. The Nyquist filter is based on the Nyquist Theory, which summarizes that only a {fraction (1/2 )}frequency bandwidth is required to transmit a digital signal at a given sampling rate.
Finally, there is a RF (Radio Frequency) converter 8 for converting the signal of an intermediate frequency band from the VSB modulator 7 into a signal of a RF band signal, and for transmitting the signal to a reception system through an antenna 9.
The foregoing VSB communication system is at least partially described in U.S. Pat. Nos. 5,636,251, 5,629,958 and 5,600,677 by Zenith Co. which are incorporated herein by reference. The 8T-VSB transmission system, which is employed as the standard digital TV broadcasting in North America and South Korea, was developed for the transmission of MPEG video and audio data. As technologies for processing digital signals develop and the use of the Internet increases, the trend currently is to integrate digitized home appliances, the personal computer, and the Internet into one comprehensive system.
FIG. 2 illustrates a related art ATSC 8T-VSB reception system 150 (xe2x80x9cVSB reception systemxe2x80x9d). In FIG. 2, there is a demodulator 11 for receiving a RF band signal through an antenna 10 and converting the RF band signal into a base band signal, a synchronizing and timing recovery (not shown) for recovering a segment synchronizing signal, a field synchronizing signal and symbol timing.
There is a comb filter 12 for removing an NTSC interference signal, and a channel equalizer 13 for correction of a distorted channel by using a slicer predictor 14. A phase tracker 15 is provided for correcting a phase of a received signal, and a Trellis decoder 16 for subjecting the phase corrected signal to Viterbi decoding. There is a data deinterleaver 17 for carrying out a reverse action of the data interleaver 3 in the transmission system, and a Reed-Solomon decoder 18 for decoding the Reed-Solomon coded signal.
The VSB reception system 150 further includes a a data derandomizer 19 for making a reverse action of the data randomizer 1 in the transmission system. Thus, the VSB reception system 150 can receive only the MPEG data, and no supplemental data. Accordingly, the development of a reception system that can receive the supplemental data as well as the MPEG video and audio data is needed. Moreover, the prediction reliability of the slicer predictor 14 in the VSB reception system 150, which predicts a signal level group, degrades in the presence of excessive channel noise or an excessive ghost.
Accordingly, the present invention is directed to a VSB reception system that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a digital VSB reception system which can receive both MPEG data and supplemental data.
Another object of the present invention is to provide a digital VSB reception system which has significantly improved performance over channel noise and ghost than the related art ATSC 8T-VSB reception system.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a VSB reception system for receiving and decoding an input signal (comprising an MPEG data segment and a supplemental data segment) transmitted from a VSB transmission system comprises a sequence generator for indicating a symbol corresponding to the supplemental data and generating a predefined sequence encoded with the supplemental data; a modified legacy VSB receiver for processing the input signal received from the VSB transmission system in a reverse order of the VSB transmission system and outputting a derandomized data signal; a demultiplexer for demultiplexing the derandomized data signal from the modified legacy VSB receiver into the MPEG data segment and an encoded supplemental data segment; and a supplemental data processor for decoding the encoded supplemental data segment from the demultiplexer to obtain the supplemental data segment.
According to one aspect of the present invention, the sequence generator includes a multiplexer for receiving and multiplexing a supplemental data dummy packet and an MPEG data dummy packet; a randomizer for randomizing an output signal of the multiplexer; a parity inserter for inserting dummy bytes to randomized data; a data interleaver for interleaving an output of the parity inserter; and a trellis coder for converting interleaved data to symbols and outputting the converted symbols without subjecting to trellis coding. Preferably, the trellis coder includes a plurality of coders and precoders for receiving the symbols and forwarding the symbols without subjecting to precoding and coding. The randomizer subjects the output signal of the multiplexer using pseudo random bytes and 0xc3x9755 to a bit-wise AND logical operation, and a result of the AND logical operation and input bits from the multiplexer to a bit-wise exclusive OR logical operation.
According to another aspect of the present invention, the symbols from the trellis coder includes two bits D1 and D0, wherein if the bit D1 is at a first logic level, a symbol corresponds to a supplemental data symbol, and if the bit D1 is at a second logic level, the symbol is an MPEG data symbol, and when the bit D1 is at the first logic level, the bit D0 is the predefined sequence being used to decode the supplemental data segment.
According to another aspect of the present invention, the dummy bytes correspond to the 20 parity bytes are dummy bytes of 0xc3x9700, and the MPEG data dummy packet produces 187 dummy bytes of 0xc3x9700, and the supplemental data dummy packet produces three dummy bytes of 0xc3x9700 corresponding to the MPEG header bytes, and 184 dummy bytes of 0xc3x97AA corresponding to the supplemental data packet.
According to another aspect of the present invention, the modified legacy VSB receiver includes a demodulator for receiving the input signal through and converting the input signal into a base band signal, and recovering a segment synchronizing signal, a field synchronizing signal, and a symbol timing from the base band signal; a comb filter for removing an NTSC interference signal from an output signal of the demodulator, if the NTSC interference signal is detected; a slicer predictor for providing a slicer prediction signal and a prediction reliability signal by using a predefined sequence from the sequence generator; a channel equalizer for correcting a distorted channel in an output signal of the comb filter by using the slicer prediction signal, the prediction reliability signal and the predefined sequence and outputting a channel equalizer output signal; a phase tracker for correcting a phase of an output signal of the channel equalizer by using the predetermined sequence and the slicer prediction signal from a trellis decoder; a trellis decoder for decoding an output of the phase tracketer using Viterbi algorithm and the predefined sequence received from the sequence generator; a data deinterleaver for deinterleaving a trellis decoder output signal; a Reed-Solomon decoder for decoding a Reed-Solomon coded signal outputted from the data deinterleaver; and a data derandomizer for derandomizing a Reed-Solomon decoder output signal.
According to another aspect of the present invention, the supplemental data processor includes an MPEG header remover for removing three MPEG header bytes from the supplemental data segment received from the demultiplexer; a null sequence remover for removing the null sequence inserted to the supplemental data packet; and a Reed-Solomon decoder for subjecting a null sequence remover output to Reed-Solomon decoding. There may be provided, a deinterleaver between the null sequence remover and the Reed-Solomon decoder for deinterleaving the null sequence remover output.
According to another aspect of the present invention, the channel equalizer includes a plurality of slicers each having a predetermined signal level detector; a feed-forward filter for receiving a comb filter output signal; a feedback filter for receiving an output signal of one of the plurality of slicers; an adder for adding output signals of the feed-forward filter and the feedback filter and outputting an added signal as a channel equalizer output signal, wherein the plurality of slicers commonly receive the added signal; a multiplexer for outputting one of the outputs of the plurality of slicers to the feedback filter in response to a control signal; and a controller for updating filter coefficients of the feed-forward filter and the feedback filter and providing the control signal to the multiplexer in response to a multiplexer output signal, the slicer prediction signal, and the prediction reliability signal, the channel equalizer output signal and the predefined sequence to select the multiplexer to output signal from one of the plurality of slicers that has the predetermined signal level detector closes to the comb filter output signal.
According to another aspect of the present invention, the slicer predictor receives the channel equalizer output signal, the predefined sequence generated from the sequence generator and information that the symbol received is of the supplemental data packet, estimates a register value of the trellis coder, calculates prediction reliability, and forwards the estimated register value and the prediction reliability signal to the controller of the channel equalizer.
According to another aspect of the present invention, the plurality of slicers includes first to third slicers for processing MPEG data symbols, and fourth to ninth slicers for processing the supplemental data symbols. The first slicer has 8 level values ofxe2x88x927, xe2x88x925, xe2x88x923, +1, +1, +3, +5, +7, the second slicer has 4 level values ofxe2x88x927, xe2x88x923, +1, +5, the third slicer has 4 level values ofxe2x88x925, xe2x88x921, +3, +7, the fourth slicer has 4 level values ofxe2x88x927, xe2x88x925, +1, +3, the fifth slicer has 4 level values ofxe2x88x923, xe2x88x921, +5, +7, the sixth slicer has 2 level values ofxe2x88x927, +1, the seventh slicer has 2 level values ofxe2x88x925, +3, the eighth slicer has 2 level values ofxe2x88x923, +5, and the ninth slicer has 2 level values ofxe2x88x921, +7. Preferably, xe2x88x927 denotes 000,xe2x88x925 denotes 001,xe2x88x923 denotes 010,xe2x88x921 denotes 011,+1 denotes 100,+3 denotes 101,+5 denotes 110, and +7 denotes 111.
According to another aspect of the present invention, with respect to the MPEG data symbols, the first slicer is selected in a low reliability case, the second slicer is selected for a high reliability case and the estimated register value is at a first logic level, and the third slicer is selected for a high reliability case and estimated register value is at a second logic level.
According to another aspect of the present invention, with respect to the supplemental data symbols one of the fourth slicer and the fifth slicer is selected in response to the predefined sequence for a low reliability case; the sixth slicer is selected for a high reliability case and the predefined sequence value and the estimated register value are at a first logic level; the seventh slicer is selected for a high reliability case and the predefined sequence value is at a first logic level and the estimated register value is at a second logic level; the eighth slicer is selected for a high reliability case and the predefined sequence value is at a second logic level and the estimated register value is at a first logic level; and the ninth slicer is selected for a high reliability case and the predefined sequence value and the estimated register value are at a second logic level.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.